AEiC 2026 accepted contributions

Note: Hovering over title provides the abstract.

Journal track

The following journal-track submissions have successfully passed the first round of review, and have been invited to be presented at the conference:

I-Segmenter: Integer-Only Vision Transformer for Efficient Semantic Segmentation
Martyna Poreba, Jordan Sassoon and Michal Szczepanski Vision Transformers (ViTs) have recently achieved strong results in semantic segmentation, yet their deployment on resource-constrained devices remains limited due to their high memory footprint and computational cost. Quantization offers an effective strategy to improve efficiency, but ViT-based segmentation models are notoriously fragile under low precision, as quantization errors accumulate across deep encoder–decoder pipelines. We introduce I-Segmenter, the first fully integer-only ViT segmentation framework. Building on the Segmenter architecture, I-Segmenter systematically replaces floating-point operations with integer-only counterparts. To further stabilize both training and inference, we propose λ-ShiftGELU, a novel activation function that mitigates the limitations of uniform quantization in handling long tailed activation distributions. In addition, we remove the L2 normalization layer and replace bilinear interpolation in the decoder with nearest neighbor upsampling, ensuring integer-only execution throughout the computational graph. Extensive experiments show that I-Segmenter achieves accuracy within a reasonable margin of its FP32 baseline (5.1% on average),while reducing model size by up to 3.8× and enabling up to 1.2× faster inferencewith optimized runtimes. Notably, even in one-shot PTQ with a single calibration image, I-Segmenter delivers competitive accuracy, underscoringits practicality for real-world deployment.

A Quantitative Type Based Framework for Synchronous System Design
Rui Chen and Ingo Sander The design process of safety-critical embedded systems is desired to be both practical and formal. These two requirements are consistently satisfied in a modern type-theorybased proof assistant/language that is increasingly accommodating general-purpose programming. A framework for embedded system design that satisfies both requirements can therefore be built upon such a proof assistant/language. In this paper, we present a framework for synchronous embedded system design that addresses both aspects (practicality and formality) by exploiting the quantitatively typed language Idris2. Specifically, we demonstrate that leveraging the expressiveness of quantitative type theory and the tagless final embedding enables an embedded domain-specific language (EDSL) named SynQ (Synchronous system design with Quantitative types) to be properly hosted in Idris2. This then allows Idris2 to be leveraged to facilitate synchronous system design (modelling, transformation, and implementation) and verification. It, hence, makes the presented framework a step towards an embedded system design methodology that is both practical and formal.

Optimizing the Deployment of Real-Time OpenMP Applications for Energy Efficiency
Federico Aromolo, Francesco Paladino, Luca Abeni and Tommaso Cucinotta Designing and deploying real-time computing pipelines efficiently on modern embedded platforms is increasingly challenging due to the growing complexity of hardware architectures, often featuring multi-core processors, frequency scaling capabilities, heterogeneous cores for enhanced power efficiency, and hardware accelerators. OpenMP is a prominent tool for parallelizing applications on multi-core platforms and is gaining increasing adoption in the domain of real-time systems. However, providing sound performance guarantees on the timing behavior of complex parallel computations organized as graph structures on heterogeneous platforms such as Arm big.LITTLE, while achieving optimal or near-optimal energy efficiency, is all but trivial. This paper tackles this problem by proposing a methodology to deploy and analyze both traditional parallel real-time applications and OpenMP parallel applications, modeled as directed acyclic graphs (DAGs) and coexisting on the same heterogeneous platform. Specifically, the approach targets heterogeneous Arm big.LITTLE-like platforms with frequency scaling capabilities, with the aim of minimizing energy consumption while guaranteeing end-to-end latency constraints via schedulability analysis. The proposed approach features an optimal solver based on a mixed-integer quadratic constrained programming formulation, and a computationally efficient heuristic to extract high-quality solutions with reduced solving time.

HELIOS: Lightweight Real-Time Scheduling with Energy Readiness Guarantees
Ruizhe Qiu, Thomas Robert, Samuel Tardieu, Laurent Pautet and Frank Singhoff Energy-harvesting embedded systems, like sensors and medical implants, must satisfy real-time constraints under strict energy limitations. Traditional schedulers, which prioritize timing over energy, often fail to produce valid schedules, particularly for nonpreemptive task models. We introduce HELIOS, a lightweight, table-driven scheduler that treats timing and energy as joint first-class constraints while supporting limitedpreemptive execution. HELIOS introduces energy readiness, ensuring jobs execute only when both temporal and energy conditions are met. The scheduling problem is formulated as an integer linear programming (ILP) problem, jointly optimizing task ordering, preemption points, and execution under energy constraints. By leveraging non-preemption and energy readiness, HELIOS maintains complexity proportional to job count. A key innovation is the use of worst-case energy footprints to guarantee safe execution via an energy readiness threshold. The table-driven runtime ensures compatibility with resource-constrained kernels. Experiments demonstrate that HELIOS achieves higher schedulability than priority-based baselines.

A Predictible Inter-Core Communication Model for AMP on Multi-Core
Sebastien Levieux, Stephane Rubini, Frank Singhoff, Lucas Mine, Philippe Plasson, Pierre-Vincent Gouel and Lee-Roy Malac-Allain Today's space systems, need to process a large amount of data in space, and therefore may use multi-core architectures. To improve timing predictability and reduce analysis complexity, they may use Asymmetric Multi-Processing (AMP). Because cores can execute subsystems supported by different operating systems, the overall system implementation requires inter-core communications implemented through portable mechanisms. In this article, we propose PrAICC (Predictible AMP Inter-Core Communication), a predictable inter-core communication model for multi-core heterogeneous AMP architectures. PrAICC has been designed to enforce timing predictability while ensuring message latency requirements. It is based on shared memory and platform-agnostic spinlocks to ensure portability, and on polling for timing predictability. We also propose a method to assess the schedulability of applications communicating with PrAICC. Our evaluations showed that the schedulability model is able to predict message latencies and task worst-case response times. The schedulability model of PrAICC is able to explore trade-offs between schedulability analysis pessimism and message latency. An evaluation on the PLATO case study determined that the best trade-off between message latencies and predictability is obtained a polling period of 100ms. With such a period, the message latency and the schedulability analysis pessimism are respectively bounded to 133ms and 48%.

Packet-Based Data Latency and Schedulability Optimization in Directed Acyclic Graphs of Multirate Automotive Cause-Effect Chains
Muhammad Tanveer Ali Ahmad, Jesus Pestana and Marcel Baunach AUTOSAR-based automotive software decomposes applications into sequences of runnables executing at different rates and linked by causal dependencies (named cause-effect chains) to realize functionalities, such as sensor-to-actuator interactions. In practice, an application contains multiple cause-effect chains that share runnables and thus form a directed acyclic graph (DAG). Meeting stringent end-to-end timing requirements (e.g., reaction time) while using resources efficiently depends strongly on how runnables are grouped into tasks and how tasks are released and scheduled. We present an automated approach that jointly determines runnable-to-task mapping, the execution order of runnables within each task, and task offsets, while preserving schedulability. To analyze end-to-end packet-based data latencies precisely, we introduce a packet-oriented method based on symbolic execution. It provides accurate and explainable timing analysis for reaction time, data age, and time disparity. Unlike existing methods that treat each cause-effect chain independently, our analysis considers the full runnable DAG and naturally supports merged multirate cause-effect chains. Together, the proposed design and analysis techniques support correct-bydesign early-stage modeling of automotive applications. Experiments on industrial case studies and automotive benchmarks show that our approach yields tighter latency estimates than state-of-the-art methods while improving explainability.

Task-to-Accelerator Mapping for Predictable OpenMP Applications
Mohammad Samadi, Tiago Carvalho, Luís Miguel Pinho and Sara Royuela OpenMP offers a high-level, portable programming model that simplifies the expression of parallelism and offloading in heterogeneous platforms, making it an ideal framework for managing task execution across CPUs and GPUs. However, as applications increasingly require predictability and multi-GPU execution, the lack of predictability in current OpenMP scheduling mechanisms poses significant challenges. Irregular workloads, variable data transfers, and dynamic resource contention often lead to inconsistent response times and reduced timing determinism. This unpredictability limits system efficiency and reliability, particularly in performancecritical and real-time domains. To overcome the challenge mentioned above, this paper proposes an efficient task-to-accelerator mapping (i.e., assigning tasks to GPU devices for execution) for multi-GPU OpenMP applications. The mechanism includes an offloading manager that operates a global queue and multiple local queues, and different heuristic algorithms that first allocate tasks to the most appropriate queues and then select the most suitable tasks from each queue. The proposed heuristics aim to balance queue loads and enhance the work-conserving property of the mapping process to minimize response time and response-time variability. The paper also presents a thorough evaluation using both synthetic graphs and graphs representative of real-world applications, showing that the proposed mapping method outperforms the other relevant mapping.

Minimal simulation interval for periodic task schedulers
Damien Guidolin-Pina, Emmanuel Grolleau, Frank Singhoff and Hai Nam Tran Simulation-based analysis is widely used to evaluate the temporal behavior of real-time systems, but its effectiveness depends on determining a finite simulation horizon after which the schedule repeats cyclically. Existing cyclicity bounds are often overly conservative or restricted to narrow classes of scheduling algorithms, and many tools still rely on seminal bounds that significantly overestimate the required simulation duration. In this paper, we introduce a new generic class of schedulers, called Resettable Deterministic Schedulers. This class strictly extends the deterministic and memoryless schedulers studied in the literature while also including non-memoryless algorithms such as Round-Robin. For this class, we establish an exact cyclicity result for work-conserving schedules of periodic task systems whose processor utilization does not exceed one. We prove that any such schedule becomes cyclic with a period equal to the system hyperperiod. The end of the first cycle is the first idle instant occurring after task releases become periodic, denoted t0. We derive a tight upper bound on this instant equal to t0+H(1+U), where U is the processor utilization, and H is the hyperperiod. When offsets are smaller than periods, the bound simplifies to H(1+U). The result requires no feasibility assumption and halves the simulation length in Cheddar.

Dependable software engineering: Can we increase trust in our components?
Marcelo Pasin, Kleiton Pereira, Titus Abele, Guilherme Piêgas Koslovski and Thomas Niederberger The complexity of the modern Software Supply Chain (SSC) introduces significant risks regarding the provenance and integrity of third-party dependencies. Current composition solutions often lack granular visibility into the artifacts they execute, relying on implicit trust in centralized registries. This paper introduces a security architecture designed to enforce explicit trust in software compositions. We define the concept of Verifiable Components, which bundle executable bytecode with cryptographically signed Software Bills of Materials (SBOMs) and audit metadata. Leveraging the nested structure of the WebAssembly Component Model, we propose a recursive verification protocol that validates the integrity of the entire dependency tree at runtime. We provide a formal proof using structural induction to demonstrate that, under standard cryptographic assumptions, our protocol eliminates the possibility of component tampering or masquerading. Furthermore, we present Wasmshield, a Rust-based prototype integrated with the Wasmtime runtime. Our evaluation shows that while generating verifiable components incurs a compilation overhead of approximately 42%, the architecture provides robust, runtime-agnostic integrity guarantees that effectively mitigate supply chain attacks.

Regular track

The following papers have been accepted in the regular papers track of the conference:

Model-agnostic Uncertainty-aware Semantic Segmentation with Conformal Risk Guarantees
Bakary Badjie, José Cecílio, Nils-Jonathan Friedrich, Norman Seyffer, Georg Jäger and António Casimiro Accurate and reliable scene segmentation is a fundamental requirement for autonomous navigation systems operating in open and dynamic environments. As these systems increasingly rely on data-driven perception modules, their safety and operational robustness hinge on well-calibrated uncertainty estimates that can explicitly control prediction errors. Most existing uncertainty-aware segmentation approaches remain architecture-specific and lack mechanisms to ensure consistent reliability across heterogeneous models and domains. This work introduces a model-agnostic conformal segmentation pipeline that enables operationally meaningful error control in real-world deployments. The proposed framework treats segmentation networks as black boxes and produces per-pixel class probabilities that are fine-tuned through deep evidential learning (DEL) to decompose aleatoric and epistemic uncertainties. We then apply pixel-wise, class-conditional split-conformal calibration to derive acceptance thresholds for user-defined target error rates. We instantiate the pipeline with DINOv2, Mask2Former, and SegFormer, and evaluate it on a newly collected Lisbon street scene (LiSS) dataset and on the COCO dataset, using a restricted set of safety-relevant classes. Results show architecture- and class-dependent in-domain uncertainty-error alignment, and that dataset shift reduces alignment, and weakens uncertainty-based filtering and conformal risk control. This motivates continuous monitoring and recalibration as a practical requirement for trustworthy segmentation in safety-critical navigation.

Discovering and Repairing Binaries C Flaws without Requiring Codebase and Instrumentation
Diogo Ferreira and Ibéria Medeiros Industrial and embedded software systems frequently integrate various third-party components sourced from diverse providers into their codebases. These systems are commonly developed in C, a language known for its lack of variable bounds checking, making it vulnerable to Buffer Overflows (BOs), which, when exploited, can cause severe damage. Consequently, the binary code resulting from vulnerable C programs is also vulnerable and remains so in the final products. Fixing these software systems is challenging because only binary code is available. This paper presents PatchBin, a binary patching tool to automatically fix BO vulnerabilities and validate the effectiveness of fixes while ensuring no new flaws are introduced. The approach involves a combination of fuzzing, reverse static analysis and static rewriting techniques to, respectively, (i) identify possible malicious inputs that can trigger BOs, (ii) find their root cause by employing reverse data flow analysis, and (iii) remove them by rewriting the binary code with effective validation, thus generating a new binary without the original flaws and new ones. Experimental evaluations with synthetic and real-world applications demonstrated that PatchBin detects and fixes BO in binary programs without introducing new vulnerabilities. The results showed that PatchBin is an important aid for industrial partners, enabling them to test and fix their products, including third-party components, without access to source code, but only to binary code.

A Certifiable Approach to Multicore Using Ada
Jose Ruiz The adoption of multicore processors in safety-critical systems, such as avionics, automotive, and rail, introduces significant certification challenges, primarily related to determinism, predictability, and interference management. This paper examines how the Ada programming language, together with its restricted tasking profiles (Ravenscar and Jorvik) and bare-metal run-time libraries, provide a robust and certifiable execution model for multicore systems compliant with guidance such as AC 20-193. By enforcing static task partitioning, fixed-priority scheduling, and a simple synchronization model, the Ada approach systematically limits interference channels and timing variability. This model enables accurate schedulability analysis, simplifies verification activities, and allows the multicore run-time library itself and the application built on top of it to be certified.

HASCO: A Hybrid AI Simulation Compiler for Semantic Accident Reconstruction
Edin Jelacic, Tiberiu Seceleanu, Cristina Seceleanu, Peter Backeman, Ning Xiong, Rong Gu, Zhennan Fei and Ali Nouri The validation of Automated Driving Systems (ADSs) has shifted from distance-based metrics to Scenario-Based Testing (SBT). Large Language Models (LLMs) have emerged as powerful tools with potential for generating vehicular scenarios at scale. However, generative models, used for direct simulation synthesis, produce inadequate output, therefore necessitating a more structured compilation approach. In this regard, we present HASCO (Hybrid AI Simulation COmpiler), a system that translates natural-language driving scene specifications into executable simulation artifacts (XOSC/XODR files) for the esmini/OpenSCENARIO ecosystem. While LLMs excel at narrative parsing, we demonstrate that direct synthesis of simulation artifacts fails in the vast majority of cases due to hallucinated physics or schema violations. To resolve this, HASCO treats scenario creation as a compilation task rather than a generative one. The pipeline supports three compilation paths: direct synthesis, a Python intermediate (via scenariogeneration), and an ontology-guided path that grounds intent into an intermediate representation (IR) before compilation. We further evaluate a self-judging mechanism for automated repair. Across six operating modes evaluated on 40 real-world accident reports, the ontology-guided compiler and Python-based compiler achieve 95% and 90% executability rates, respectively (compared to 5% for direct synthesis). Additionally, we evaluate outputs on semantic fidelity, positioning HASCO as a robust tool for forensic scene reconstruction.

A Rust Framework for Real-Time Parallel Programming
Hugo Silva, Tiago Carvalho and Luis Miguel Pinho Real-time systems increasingly rely on parallel execution to meet performance and timing requirements. While several programming languages provide mechanisms for combining real-time and parallel programming, Rust currently lacks dedicated frameworks that address both aspects in an integrated way. In previous work, we proposed a high-level design of a framework for real-time parallel programming in Rust. In this paper, we describe the design of a prototype implementation of this framework as a Rust library. The prototype provides abstractions for creating and managing real-time threads with priorities, as well as thread pools that enable structured parallel execution while respecting priority-based scheduling. We describe the architecture of the prototype, its implementation and illustrate its use through examples. This implementation demonstrates the feasibility of supporting real-time parallel programming patterns in Rust and serves as a foundation for future extensions of the framework.

Task-Based Constant Bandwidth Server in the Zephyr Operating System
Alexander Paschoaletto, Paulo Baltarejo Sousa, Luis Miguel Pinho and Tiago Carvalho The Constant Bandwidth Server (CBS) is a widely used method to support aperiodic soft real-time tasks in a system that uses dynamic scheduling algorithms, such as Earliest Deadline First (EDF), while providing end-to-end temporal guarantees through bandwidth reservation. We have recently proposed an approach to integrate CBS with the open-source real-time operating system, Zephyr, which involves developing CBS as a separate kernel component that can be shared by multiple execution contexts. In this paper, we propose an alternative approach, which provides each task with a dedicated CBS instance, which enables fine-grained control over task execution. The paper also presents a richer support for EDF scheduling in Zephyr, which is used to support the Task-Based CBS. The proposed method is validated through test cases, demonstrating its efficiency in supporting aperiodic real-time tasks with bandwidth constraints in Zephyr.

A Flexible Ada Framework for Jitter-Sensitive Mixed-Criticality Real-Time Systems
Sergio Sáez Barona and Jorge Real Sáez Real-time systems often require combining time-triggered (TT) and event-triggered (ET) execution models to balance predictability and flexibility. Previous work proposed a unified framework supporting both paradigms, enabling the integration of jitter-sensitive activities within a static TT schedule while preserving the responsiveness of ET execution. However, that framework did not address the requirements of mixed-criticality systems (MCS), where tasks may exhibit different execution-time assumptions depending on the system criticality level. This paper extends the original framework to support mixed-criticality workloads. First, the task model is enhanced to incorporate multiple execution-time estimates per job, allowing tasks to adapt their behaviour across criticality levels, including the possibility of selectively disabling jobs. Second, the TT scheduling model is extended to support criticality-aware execution, introducing adaptive slot durations, application-level overrun handling, and mechanisms to control the system criticality level at run time. Third, the framework preserves the semantic consistency of multi-frame tasks under criticality-level changes by defining a clear separation between system-wide and task-local criticality. Additionally, the mode-change mechanism is extended to support timed mode changes, enabling precise control over plan transitions and facilitating synchronisation across distributed schedules. The proposed approach maintains the predictability of TT execution while providing the flexibility required to support mixed-criticality behaviour. An execution example illustrates the applicability of the framework and the interaction between its main components.

Work-in-progress track

The following work-in-progress papers have been accepted at the conference:

A Layered Approach to Simulation-Based Validation in Robotic Applications
Gema Rincon, Carlos Fernando Nicolas, Irune Yarza and Tomaso Poggi The use of collaborative robots has increased in recent years. As these robots operate alongside humans or share the same workspace, validating safety-critical situations becomes challenging because testing them in real environments may endanger people. Simulation provides a promising alternative, but an important challenge is the gap between simulated and real environments caused by factors such as lighting variations or dynamic changes. This work proposes a theoretical approach to improve simulation-based validation of sagety-critical robotic applications by focusing on environment parameter variability and exploring generative AI to generate diverse test scenarios. The approach is discussed in the context of a robotic application in a dining room environment.

DELEGATE-RATS: Delegated Group Attestation for Trust and Efficiency in RATS
Maria Gomes da Silva, João Garcia, André Souto, Pedro Ferreira, António Casimiro and José Cecílio Remote attestation is a fundamental mechanism for establishing trust in distributed systems, but existing solutions, such as the RATS architecture, struggle to scale in large hierarchical deployments. This paper presents a delegated, multi-tier attestation architecture that preserves compatibility with RATS while decoupling the authoritative root of trust from the operational workload of evidence evaluations. The design introduces an authoritative core composed of a BFT trust anchor, a Certificate Authority, and a Root Verifier responsible for policy ingestion and global trust decisions, while allowing previously attested devices to be promoted as local verifiers for their descendants. Attestation thus proceeds hop-by-hop along the topology, with delegated verifiers enforcing centrally defined policies and reporting compact results upstream. An experimental evaluation using linear and tree-structured topologies demonstrates that the proposed architecture significantly reduces the load on the root verifier and achieves attestation times that are lower or comparable to those of a baseline RATS deployment, while continuing to operate as the number of devices increases and the centralized baseline can no longer be sustained.

Contract-Based Runtime Monitoring for a Smart House Digital Twin
Muhammad Naeem, Cristina Seceleanu and Tiberiu Seceleanu Digital Twins (DTs) are increasingly used to support monitoring, prediction, and decision-making in cyber-physical systems. However, ensuring the reliability of DT-based systems remains challenging, particularly when data-driven models are used for control and prediction. The D-RODS project addresses this challenge by developing a framework for dynamic and robust distributed DTs that integrates artificial intelligence with verification and validation techniques. In this work-in-progress paper, we present a prototype that applies the D-RODS framework to a smart house scenario. The system maintains the temperature of a physical environment within recommended limits while enabling monitoring and automated control through a DT implemented in MATLAB and connected to the physical system through a supervisory application. The application incorporates a contract-based observer that verifies input signals and controller decisions at runtime. When violations are detected, control is switched from the physical controller to the DT controller. Initial experiments show that the DT controller closely follows the behavior of the physical controller, while the temperature prediction model exhibits deviations in some scenarios.

Industrial track

The following industrial presentations have been accepted at the conference:

Implementing Ada 2022 Parallel Constructs
S Tucker Taft, Ethan Luis McDonough and Richard Wai The parallel features of Ada 2022 remain unimplemented by the major Ada compiler vendors. In the summer of 2025, we took advantage of the Google Summer of Code program to support a project by a new college graduate (and one of the co-authors), to build an initial implementation of the primary Ada 2022 parallel constructs, parallel loops and parallel blocks, as an enhancement to the GNAT GCC Ada front end. The implementation was successful and is now available as part of a public GitHub repository established for the Ada Rapporteur Group, a repository intended for users interested in trying out otherwise unavailable Ada 2022 features.

Generative Digital Twin Framework for Reliable and Robust AI-Powered Prognostic Systems
Zafer Yigit, Hakan Forsberg and Masoud Daneshtalab Reliable and robust operation of heavy-duty construction equipment is critical for maintaining productivity and minimizing costs. However, developing robust Prognostics and Health Management (PHM) systems for such machines remains a challenge due to the limited availability of labelled failure data. This research investigates a PHM framework driven by digital twins that combines machine learning, physics-informed modelling, and synthetic data generation. The proposed approach uses digital twins of the engine to produce physically consistent datasets that support training of anomaly detection and prognostic models. In addition, ongoing work explores physics-informed recurrent architectures and generative scenario modeling to further improve model robustness and data diversity for industrial PHM applications. Early results indicate that incorporating physics-informed dynamics improves model robustness and prediction stability compared to purely data-driven approaches.

Finding ODD gaps
Martin Skoglund Operational design domains (ODDs) are central to the specification, verification, and assurance of automated driving systems (ADSs). While several standards and data models support structured ODD descriptions, practical methods for assessing whether collected evidence adequately covers an intended ODD remain limited. This enables enumerating discrete operating conditions, comparing an intended ODD with an accumulated test ODD derived from evidence, and identifying operational design gaps. The contribution is a concise, machine-interpretable workflow for transforming an ODD specification into coverage analysis and targeted, gap-driven data collection.

System Architecture for AI-Enabled Monitoring in Distributed Indoor Farming Systems
Sepehr Mousavi and Baran Curuklu Distributed indoor farming systems are increasingly implemented as software-intensive cyberphysical systems integrating sensors, edge computing, and AI-driven monitoring. In controlled environment agriculture (CEA), this paradigm is particularly visible through the concept of on-site farming where compact production units are deployed directly inside commercial environments such as grocery stores, retail, restaurants, and corporate buildings. While these systems offer advantages in freshness, logistics reduction, and transparency of production, they introduce new challenges related to remote plant performance monitoring and steering across distributed installations. Traditional monitoring approaches relying on environmental proxies, manual inspection or post-harvest measurements do not scale effectively in multi-site operational contexts. This work explores the design of software-intensive monitoring architectures combining image-based and optical sensing with AI-driven analytics for distributed indoor farming systems. Using the operational context of Swegreen AB as an industrial case, the research investigates how computer vision pipelines, edge computing, and distributed learning architectures can provide scalable monitoring and optimization capabilities across geographically distributed farming units. Particular attention is given to the system architecture, data pipelines, and edge–cloud interaction required to operate these systems reliably in real-world commercial environments. The goal is to enable robust software-driven monitoring that improves system observability, yield predictability, and operational reliability across distributed cyber-physical farming installations.