Invited Speakers

Keynote Talk: Strategies to build safety relevant high-performance HW/SW platforms for critical embedded systems

Dr. Francisco J. Cazorla, Barcelona Supercomputing Center
Dr. Jaume Abella, Barcelona Supercomputing Center

Wednesday, 12 June, 9h15


The increasing autonomy requirements of critical embedded systems (CES) in a variety of domains, including automotive, space, avionics, and robotics, rely on AI software. The high-performance requirements of AI software call for the adoption of MPSoCs capable of providing the required performance levels. However, this trend towards more complex hardware and software in CES poses significant challenges on functional safety. Challenges relate to non-obvious interactions across applications and tasks, with arbitrarily large impact on performance and also functional correctness. This calls for hardware and software solutions that mitigate these risks.

In this talk we will delve into two sets of technologies to mitigate the risks associated to the increasing complexity of the platforms needed for future CES, namely (1) software-only solutions based on advanced platform testing and configuration, and (2) hardware modules providing observability, controllability, and support for safety measures.

In terms of software-only solutions, we will present methods and technologies to identify key performance features relevant for multicore interference in high-performance MPSoCs, and to configure QoS knobs to mitigate interference while preserving performance, as well as software technologies to generate stressful scenarios relevant for Worst-Case Execution Time (WCET), and to enable WCET estimation in the context of multi-provider software with IP restrictions.

In terms of hardware solutions, we will present our strategy to extend high-performance MPSoCs with features to enable their use in safety-relevant scenarios without impacting meaningfully performance. In particular, we will present several modules for advanced multicore observability and quota control (SafeSU), flexible performance testing (SafeTI), multiple flavors of diverse redundancy (SafeDM, SafeDE, SafeLS), and platform monitoring and reconfiguration (SafeTCO).

Short Bios

Dr. Fracisco J Cazorla, co-leads the CAOS research group at BSC. His area of research includes the safe use of aggressive processor designs (e.g multicore designs) in critical embedded systems. Dr. Cazorla has led 3 European Projects (PROARTIS, PROXIMA, and MASTECS) and has been ERC Consolidator Grantee (SuPerCom) on this topic. He has also led several projects funded by the European Space Agency (ESA). He was the confounder of Maspatechnologies, a BSC spin-off specialized is software verification technologies of the temporal behavior of multicore processors.

Dr. Jaume Abella, co-leads the CAOS research group (embedded systems group) at BSC. Dr. Abella leads the HE SAFEXPLAIN project, and is (has been) the PI at BSC of another 10 EU projects on enabling the use of high-performance hardware and software, as well as AI in safety-critical systems. Jaume co-leads the OpenHW Group Safety&Security Task Group and RISC-V International SIG-Safety. Dr. Abella holds 15 patents issued, has published around 250 papers in peer-reviewed conferences and journals, has co-advised 15 PhDs and 20 Master theses, and co-founded a successful spinoff providing software services in avionics and automotive.

Panel: AI for Safety-Critical Systems: How "I" Should the AI be?

Prof. Dr. Cristina Seceleanu, Mälardalen University

Invited experts
Prof. Dr. Kerstin Bach, Norwegian University of Science and Technology
Dr. Irune Yarza, Ikerlan
MSc. Marta Barroso, Barcelona Supercomputing Center

Thursday, 13 June, 9h15

Short Bios

Prof. Dr. Cristina Seceleanu is Professor of Computer Science and Docent at MDU, Networked and Embedded Systems (NES) division, and research leader of the Computer and Data Science (CDS) research direction. She received a MSc. in Electronics from Polytechnic University of Bucharest, Romania, in 1993, and a Ph.D. in Computer Science from Åbo Akademi and Turku Centre for Computer Science, Åbo/Turku, Finland, in Dec. 2005. Her research focuses on developing formal models and verification techniques for designing predictable real-time, adaptive and autonomous systems.

Prof. Dr. Kerstin Bach is a professor of Artificial Intelligence at the Norwegian University of Science and Technology (NTNU) and holds the role of Research Director at the Norwegian Research Center for AI Innovation (NorwAI). She commenced holds a PhD from the university of Hildesheim and worked as a researcher at the German Research Center for AI (DFKI), where she developed decision support systems for various industries. Throughout her career, Kerstin has undertaken significant responsibilities, notably as the driving force behind myCBR, an open-source tool adopted in research and industry projects across Europe. Following the completion of her Ph.D., Kerstin joined Verdande Technology, a Trondheim-based AI startup, where she held roles as both a research scientist and software engineer before eventually joining the faculty at NTNU.

Dr. Irune Yarza is an Industrial Electronic and Automation Engineer by the University of Deusto, master's in advanced electronic systems by the ETSI in Bilbao (2016), and Ph.D. in Computer Science by the University of Oldenburg (2019). She joined IKERLAN as a researcher in 2015, becoming part of the Real-Time Systems team in the Reliable Embedded Systems area. She obtained her Ph.D. in Computer Science at the University of Oldenburg (Germany), completing stays at OFFIS - Institute for Information Technology. Subsequently, she has been part of the Cybersecurity and Safety Systems area within the Cybersecurity and Safety Methodologies team. With her participation in European projects, her main research activity today focuses on functional safety. Additionally, she has participated in various R&D projects in the field of real-time safety-critical embedded systems, mainly in the lift and automotive sectors. She holds the Functional Safety Engineer certification from TÜV Rheinland according to the ISO-26262 and IEC-61508 standards.

MSc. Marta Barroso Isidoro began her academic journey with a Bachelor's in Computer Science at UPC, followed by a Master's in AI, focusing her thesis on utilizing biosensors in psychiatric hospitals to monitor patient movement, particularly when they leave their beds. Her current role at the Barcelona Supercomputing Center involves working with the HPAI research group, where she applies her expertise in Machine Learning and Deep Learning to projects like ciberes-uci-covid and KnowlEdge, generating valuable insights for healthcare. Marta's problem-solving style emphasizes attention to detail and innovation, using advanced computational methods to tackle healthcare challenges. She's also pursuing research in large language models to contribute to this field.

Invited Talk: Simplifying the life-cycle management of complex application workflows

Dr. Rosa Maria Badia, Barcelona Supercomputing Center

Wednesday, 12 June, 13h30

Find here the slides!


With Exaflop systems already here, high-performance computing (HPC) involves larger and more complex supercomputers. At the same time, the user community is aware of the underlying performance and eager to leverage it by providing more complex application workflows to leverage them. Moreover, current application trends aim to use data analytics and artificial intelligence combined with HPC modelling and simulation. However, the programming models and tools are different in these fields, and there is a need for methodologies that enable the development of workflows that combine HPC software, data analytics, and artificial intelligence.

PyCOMPSs is a parallel task-based programming in Python. Based on simple annotations, it can execute sequential Python programs in parallel in HPC clusters and other distributed infrastructures. PyCOMPSs has been extended to support tasks that invoke HPC applications and to combine them with Artificial Intelligence and Data analytics frameworks. PyCOMPSs also supports fault-tolerance at the task level, giving flexibility to cancel part of the workflow due to faults. It also implements a checkpointing and restart feature to support major failures.

In addition, to help with the overall workflow lifecycle management, we have defined the HPC Workflows as a Service (HPCWaaS) methodology that aims to provide tools to simplify the development, deployment, execution, and reuse of workflows. In particular, we will describe the Container Image Creation service, which automates the creation of container images tailored to a specific HPC platform.

Short Bio

Dr. Rosa M. Badia holds a PhD on Computer Science (1994) from the Technical University of Catalonia (UPC). She is the manager of the Workflows and Distributed Computing research group at the Barcelona Supercomputing Center (BSC). She is considered one of the key researchers in Parallel programming models for multicore and distributed computing due to her contribution to task-based programming models during the last 15 years. The research group focuses on PyCOMPSs/COMPSs, a parallel task-based programming distributed computing, and its application to the development of large heterogeneous workflows that combine HPC, Big Data, and Machine Learning. The group is also doing research around the dislib, a parallel machine learning libray parallelized with PyCOMPSs. Dr. Badia has published near 200 papers in international conferences and journals on the topics of her research. She has been very active in projects funded by the European Commission in contracts with industry, and she has been the PI of the EuroHPC project eFlows4HPC. She is a member of HiPEAC Network of Excellence. She received the Euro-Par Achievement Award 2019 for her contributions to parallel processing, the DonaTIC award, category Academia/Researcher in 2019 and the HPDC Achievement Award 2021 for her innovations in parallel task-based programming models, workflow applications and systems, and leadership in the high performance computing research community. In 2023, she has been invited to be a member of the Institut d'Estudis Catalans (Catalan academy).

Invited Talk: The Compute Continuum: An Efficient Use of Edge-to-Cloud Computing Resources

Dr. Eduardo Quiñones, Barcelona Supercomputing Center

Wednesday, 12 June, 15h00

Find here the slides!


There is the need for gluing edge, cloud and HPC technologies into a unified compute continuum solution to manage and analyse the complete lifecycle of data, and on top of it, provide new frameworks to enable users to easily describe complex data analytics workflows to be deployed on the compute continuum.Towards this direction, this presentation will identify the three main key challenges that are needed to be addressed: (1) optimize current data infrastructures and AI & Big-data frameworks to jointly address data processes and analytics methods; (2) develop orchestration techniques to select the most appropriate set of computing resources; and (3) increase the interoperability between the most common programming practices and execution models used across the compute continuum, i.e., HPC, edge and cloud computing resources, to effectively address the diverse characteristics of data.

Short Bio

Dr. Eduardo Quiñones is a senior researcher in the Department of Computer Science at the Barcelona Supercomputing Center (BSC). He received his Ph.D. in computer science from the Universitat Politècnica de Catalunya (UPC) in Barcelona in 2008. His research interests are strongly tied to next generation industry requirements for critical real-time systems spanning future processor architecture, operating system and compiler designs. Eduardo has experience in international research projects, including European Projects and European Space Agency (ESA) projects. He collaborates with key multinational companies in the avionics, automotive and space domains, including Airbus Defense and Space, Denso, Infineon, Kalray, Thales and Honeywell, and with the main European research institutions.
Specialties: High-performance platforms for critical real-time embedded systems, many-core heterogeneous architectures, parallel execution, probabilistic timing analysis.